1. Field of the Invention
The present invention relates to an analog-digital converter of the SAR type and a method of employing it.
2. Description of the Related Art
An analog-digital converter of the SAR (Successive Approximation Register) type is illustrated in a schematic manner by FIG. 1. It comprises elements for the quantization of an analog input parameter to be converted, in the form of a digital-analog converter DAC (which includes a reference voltage source VREF) and a comparator COMP, and a logic unit LOG (which includes a register REG) with timing and control functions connected to the converter DAC and the comparator COMP by means of a control bus CTRLBUS. A signal of timing or clock pulses (CLOCK) is applied to a terminal CK of the logic unit. An input voltage to be converted VIN is applied to the converter DAC and a conversion request signal CONVREQ is applied to a starting terminal STR of the logic unit LOG. A sequence of clock-pulse timed signals activates the converter DAC and the comparator COMP and makes possible the loading of the sample VIN to be converted. The register REG is set to a digital value corresponding to the centre of the scale of the conversion range (10000000 in the case of an 8-bit register). The converter DAC therefore furnishes an output voltage of VDAC=VREF/2. The comparator COMP compares this voltage with the voltage VIN and provides the result of the comparison to the logic unit. When VIN>VDAC, the comparator output is a logic “1” and the most significant bit of the register remains at “1”. But when VIN<VDAC, the output of the comparator is a logic “0” and the most significant bit of the register is switched to a logic “0”. The next bit of the register is then set to “1”, followed by another comparison with the same criterion, and this is continued until the least significant bit has been examined. At this point the conversion is finished and the register contains the digital code, in this example consisting of 8 bits, corresponding to the input voltage VIN. This code is available at the output OUTBUS of the logic unit LOG and the register REG, which is the output of the converter.
A typical analog-digital converter of the SAR type uses a digital-analog converter DAC of the switched capacitor type, as shown in FIG. 2. For simplicity of representation, the figure shows a converter having a resolution of only 5 bits, but it is well known that converters with a much larger number of bits are used in actual practice, 12 being a case in point. The converter of FIG. 2 comprises an array 10 of six capacitors b1–b6 with each of which there is associated a two-way switch SW1–SW6. The capacitors b5 to b1 are weighted in binary code, i.e., they have capacitances that increase in accordance with a factor 2i, where i may vary between 0 and 4. The sixth capacitor, b6, has a capacitance equal to that of the capacitor b5 and serves to assure that the sum of the capacitances of the array will be exactly double the capacitance of the capacitor b1.
One electrode of each of the capacitors is connected to a common terminal NS. The two-way switches serve to connect the other electrode of each of the capacitors selectively to a first terminal, indicated by NC, or a second terminal, indicated by the ground symbol. The terminal NS may be connected to ground or may be left free by means of a one way switch S2. By means of a two-way switch S1, the terminal NC may be selectively connected to an input terminal 11 to which there is applied the input signal VIN of the analog-digital converter or to a reference terminal 12 on which there is present the reference voltage VREF (provided by the voltage source included in the block DAC in the scheme of FIG. 1).
The terminal NS is connected to the non-inverting input terminal of an operational amplifier 13 that performs the function of the comparator COMP of FIG. 1. The inverting input terminal of the operational amplifier 13 is connected to ground. The output OutCmp of the comparator is connected to the logic unit LOG. The bus CTRLBUS issuing from the logic unit LOG carries control signals for the two-way switches SW1–SW6, the one-way switch S2 and the two-way switch S1 to operate them in accordance with a predetermined timing programme and as a function of the comparator output. It is to be understood that the two-way switches and the one-way switch are in practice constituted by controllable electronic connection devices, for example MOS transistors or combinations of MOS transistors. The logic unit LOG records the position of the switches SW1–SW5 in the register REG in order to furnish on the output OUTBUS a digital code corresponding to the analog input signal VIN.
Briefly described, the converter functions as follows:
in a first phase, the sampling phase, the switches are controlled by the logic unit LOG in such a manner as to be in the positions shown in FIG. 2, i.e., with the terminal NC connected by means of the switch S1 to the input terminal 11, to which there is applied the signal VIN to be converted, with the terminal NS connected by means of the switch S2 to ground and with all the lower electrodes of the capacitors connected by means of the switches SW1–SW6 associated with them to the terminal NC, so that all the capacitors are charged to the voltage VIN (referred to ground);
in the subsequent phase, the storage phase, the logic unit LOG causes the switch S2 to open and then causes the switches SW1–SW6 to switch and thus to connect the lower electrodes of all the capacitors to ground, with the result that the common terminal NS of the array 10 will assume the voltage −VIN (referred to ground);
at this point the logic unit LOG commences the operations typical of SAR technique to identify by means of successive attempts the values of the bits that make up the binary code that represents the sample of the analog input voltage; each “attempt” is carried out in one period of the clock signal; more particularly,
during the high-level part of the clock signal, with a view to finding the most significant bit (first “attempt”), the lower electrode of the capacitor b1 of greater capacitance (C) is connected to the terminal 12, which is at the reference voltage VREF, by means of the switching of the switches SW1 and S1: this causes the voltage of the terminal NS to rise from −VIN to −VIN+VREF/2; the reference voltage VREF is chosen in such a way as to have a value equal to the maximum voltage VIN that can be converted;
during the low-level part of the clock signal the comparator COMP carries out a comparison: when the voltage −VIN+REF/2 is negative, the comparator COMP will have a low output signal and the logic unit LOG will maintain the switch SW1 in the position in which the lower electrode of the capacitor b1 is connected to the reference terminal 12 (VREF) and will transmit this position information to the register REG as corresponding to bit 1;
on the other hand, when the voltage −VIN+VREF/2 is positive, the comparator COMP will have a high output signal and the logic unit LOG will bring the switch SW1 back into the position in which the lower electrode of the capacitor b1 is connected to ground and will transmit this position information to the register REG as corresponding to a bit 0;
the same operation is carried out for the capacitor b2 in a subsequent period of the clock signal to find the second bit (second “attempt”) and then repeated for all the remaining capacitors, excluding only the last, b6, which remains connected to ground for the entire duration of the SAR operations;
at the end the register REG will contain five bits that represent the final position of the switches SW1–SW5 and the binary code corresponding to the value of the sample input voltage VIN.
In the realization of a switched-capacitor converter of the type described above the source of the reference voltage VREF is in practice constituted by a buffer connected to a biasing circuit. This circuit is made in such a way as to generate a stable and precise reference voltage, substantially insensitive to temperature variations, supply voltage fluctuations of the integrated circuit and the variability of the manufacturing parameters. The buffer is typically constituted by an operational amplifier having a pass band sufficiently wide to satisfy the switching speed requirements of the converter and a capacity of supplying current such as to satisfy the power requirements of the converter.
Considering the functioning of a typical switched-capacitor converter in accordance with FIG. 2, one should note that the phase of charging the capacitors of the converter DAC in the subsequent operations (or “attempts”) to determine the values of the bits to be sent to the output register is decisive for the purposes of dimensioning the reference voltage buffer. In particular, the buffer must be capable of charging the capacitors during one clock pulse, i.e., during the high part of the clock signal, which in the case of a typical clock signal with a duty cycle of 50% is half the period. The time available for charging the capacitors may be even shorter in actual practice if one bears in mind the fact that when one sets out to fabricate an integrated circuit containing a clock generator designed for a nominal duty cycle of 50%, one may obtain a real duty cycle comprised between 40% and 60% due to the effect of the variability of the manufacturing parameters. The designer must therefore take account of this uncertainty regarding the value of the duty cycle and dimension the buffer for the worst possible conditions.
A typical field of application of analog-digital converters of the type described above is that of cellular telephones. A strongly felt need when designing these telephones, as also many other types of battery-operated portable equipment, is to reduce the consumption of electric energy to a minimum. Analog-digital converters are among the devices that make a significant contribution to the consumption of the equipment. In particular, the contribution that the buffer makes to the overall consumption of the integrated circuit of which it forms part is always considerable and, in many cases, constitutes the greater part of the consumption of the converter.